MENTOR FORUM 2019

mentor forum 2019

New Era of IC to Systems Design
September 3, 2019

【早鳥這廂有禮啦】

9月3日前50名完成報到者，不用抽獎直接送7-11商品卡，最實用的禮品讓最早到現場的您隨時補充元氣!

【攤位任務獎】

只要您在9月3日下午2:40前將集滿10個攤位導覽印章的抽獎券投入抽獎箱中，即有資格參加「攤位任務」抽獎活動，把小米米家掃地機器人帶回家！

Welcome

New Era of IC to Systems Design

IC設計日益複雜，如何實現以更快的速度，更具成本效益的方式開發更出色的產品成為當今電子設計領域不斷面臨的挑戰。Mentor, a Siemens Business持續提供各種創新產品與解決方案。因應數據時代的來臨為物聯網IoT、人工智能AI、汽車電子Automotive IC、複雜系統單晶片Complex SoC、以及先進半導體Advanced semi等科技應用提供晶片的布局設計驗證、良率提高、模擬、分析除錯、自動化協同設計、分析平台及工具以解決IC設計、封測之難題。台灣的半導體先進製程邁入 7奈米(nm) ，衝刺 5nm，建設3nm的時局，即是宣告將從單純IC設計進入系統設計的新時代來臨。

今年我們邀請到TSMC、Samsung、Microsoft Azure、群聯電子及聯發科等行業專家電子工程設計精英齊聚一堂，共同探討影響半導體設計的最難挑戰，最新應用，最熱趨勢及最新技術及最有效解決方案。上午場次是由行業精英來為前瞻趨勢及發展方向做定調，下午分為五個技術主題：物聯網IoT、人工智能AI、汽車電子Automotive IC、複雜系統單晶片Complex SoC、以及先進半導體Advanced semi。

一場不容錯過的年度盛會，IC設計的知識饗宴，Mentor, a Siemens Business期待您撥冗出席共襄盛舉！

Keynote Speaker

Joe Sawicki

Executive VP, Mentor IC EDA of Mentor, a Siemens Business.

Keynote Speaker

K.S. Pua

CEO, PHISON Electronics Corp.

Keynote Speaker

Alex Chang

Director, Computing and Artificial Intelligence Technology Group, MediaTek Inc.

Agenda

START	END	Track 1 IoT	Track 2 AI	Track 3 Automotive IC	Track 4 Complex SoC	Track 5 Advanced Semi
09:00	09:50	Registration/welcome coffee / Vendor Fair
09:50	10:00	Welcome Speech
10:00	10:35	Keynote I: Semiconductor Design in the Machine Learning Era - Joe Sawicki, Executive VP, Mentor IC EDA, Mentor, a Siemens Business
10:35	11:10	Keynote II: IC Design Still IC Design? - K.S. Pua, CEO, PHISON Electronics Corp.
11:10	11:45	Keynote III: How Edge AI Technology Is Redefining Smart Devices for the Future - Alex Chang, Director, Computing and Artificial Intelligence Technology Group, MediaTek Inc.
11:45	11:55	Break-out session Introduction - Lincoln Lee, PacRim Technical Director, Mentor, a Siemens Business
11:55	13:00	Lunch / Vendor Fair
13:00	13:45	Mentor's implementation flow for Edge smart IoT Mixed Signal Ics	An Emulation Strategy for Artificial Intelligence and Machine Learning Devices	Mentor Safe IC - End-to-end Functional Safety Solution addressing ISO-26262	Plug and Play SoC DFT architecture	How to Reduce DRC Closure Time Enabling Faster SOC Tapeouts
13:45	14:30	Solido Solutions – Delivering Variation Aware Design and Characterization Powered by Machine Learning	DFT Enablement for AI device	Plan Driven and Requirements Driven Verification	Automated Formal Apps for SoC Verification	Calibre and the Cloud: Unlocking Massive Scaling TSMC, Microsoft Azure co-present
14:30	14:50	Coffee Break / Vendor Fair
14:50	15:35	Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform	Leveraging HLS IP and Reference Designs to Accelerate AI and Image/Signal Processing	The PAVE360 Program offers Chip-to-Vehicle verification continuity methods combining electronics, sensors and powertrain modeling for faster development of Safer Autonomous Vehicles	A Metrics-Driven Power Regression Methodology - Samsung's Power and Redundant Power analysis in RTL stage using PowerPro Samsung co-present	Calibre LVS: Innovation beyond a Verification Flow; A Complete Platform to Downstream Tools
15:35	16:20	Predicting Silicon Performance with High Accuracy Parasitic Extraction	How Advanced 3D Package Enables High Performance AI devices	The next level of test quality - silicon results	Have Your Cake and Eat It Too: Questa inFact PSS-Infused Apps Make the Most of Your UVM	Calibre PERC: Sign-Off Solutions for Circuit Reliability
16:20	16:30	Closing Comment / Lucky Draw

Registration

本活動報名截止日為8月23日(五)。主辦單位將視報名狀況提前或延後線上報名時間。
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Keynote

Joe Sawicki

Executive VP, Mentor IC EDA of Mentor, a Siemens Business.

Bio: Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Mentor IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.

Semiconductor Design in the Machine Learning Era

Abstract: Twin thrusts are driving significant growth in Machine Learning (ML) applications in the semiconductor industry. The first is a surge in venture capital for ML-based semiconductor design, focused on a wide range of markets such as transportation, energy, connected cities, cloud computing, and smart manufacturing. The second is the incredible algorithmic opportunity ML offers EDA tools. Joe Sawicki, Executive Vice President of Mentor IC EDA, will survey the impact of ML on semiconductor design. After an overview of all the exciting growth areas, Joe will discuss how ML expands design requirements and demands at the algorithmic level. He will also examine the impact of ML on EDA tool development in the key areas of intelligent pattern analysis and the ability to analyze the enormous amount of data generated in simulation and test.

K.S. Pua

CEO, PHISON Electronics Corp.

Bio: KS Pua is the Founder, Chairman and CEO of Phison Electronics. He was born in a farming community Sekinchan in Selangor, Malaysia in 1974. At the age of 19, went to Taiwan with just US$4,000 in his pocket. With no relatives to help him, his only dream was to study hard, graduated from National Chiao Tung University (NCTU) in Hsinchu, Taiwan in 1997 and earned Master’s from NCTU in 1999. Mr. Pua and his four friends founded Phison Electronics Corp. in Taiwan. He designed and produced the world’s first single chip USB flash controller with other founders. Under his lead, the company has become a global leader in NAND Flash controller IC and storage solutions.

As an entrepreneur, Mr. Pua is a successful high-teck entrepreneur and the recipient of the Ten Outstanding Young Malaysian Awards, and received Outstanding Young Entrepreneur Award, Outstanding Young Manager Award and The President Award of National Management Excellence Award from the Government. He was elected as Fellow of Chinese Society for Management Of Technology in 2009. In 2010, Phison enjoyed turnover of US$1.06 billion, and had become the largest market of flash-memory related products in Asia-Pacific area and was named 65th in U.S. magazine Bloomberg Businessweek’s Tech 100. From 2015 to present, production value of Phison were ranked 3rd of IC Design Houses in Taiwan IC design industry.

IC Design Still IC Design?

Abstract: Today’s IC design is very different from 20 years ago. With more complicated features and minimized sizes trend, system-oriented and application-oriented IC design has become a critical topic that IC design companies need to re-consider for future development.
Combining more than 20 years of experiences in NAND controller IC design and storage solutions, PHISON will share how we think of the future of IC design. Additionally, from the experiences working in various NAND applications and industries, a new way of shaping IC design industry will be shared.

現今的IC設計與20年前的IC設計已大不同。隨著功能複雜化以及尺寸極小化的趨勢，透過完整系統整合概念以及應用導向的IC設計方向已逐漸成為顯學。群聯電子 (PHISON) 集結超過20年的NAND控制晶片IC設計及儲存系統整合經驗，發展至今已成為全球最大的獨立快閃記憶體控制晶片IC設計及儲存解決方案整合領導者，提供包含SSD、UFS、eMMC、SD、USB等全方位的NAND儲存解決方案，且含括從消費應用、嵌入式應用、工控寬溫應用、車載系統、企業伺服器、資料中心等各種應用領域。透過獨步全球的彈性營運模式以及高度客製化的系統整合服務，群聯電子能協助並滿足各式各樣的NAND儲存需求及應用，加速NAND儲存的普及率，讓終端的使用者享受快閃記憶體所帶來的可靠及高效能體驗。

Alex Chang

Director, Computing and Artificial Intelligence Technology Group, MediaTek Inc.

Bio: Alex Chang is the Director of the Computing and Artificial Intelligence Technology Group at MediaTek. Alex Chang is responsible for essential technology development such as Artificial Intelligence (AI) algorithm and system software framework. Currently, he is leading the establishment of the MediaTek AI technology that has powered a wide range of MediaTek products.

In his early career, Alex led the development of MediaTek smartphone and home entertainment SOC. Later when smartphone drives the need of high speed and low power computing, he committed to high speed CPU and GPU design and implementation. He also established signal integrity and power integrity signoff methodologies to secure Ghz design and implementation. It enabled multi-core mobile SoC achieving the best balance of performance and energy efficiency, which has been widely used in most MediaTek mobile SoCs that now power hundreds of millions of mobile devices worldwide.

Alex has more than 15 years of experience in semiconductor SoC development. He earned his M.S. degree and B.S. from the Institute of Computer Science, National Tsing Hua University, Taiwan.

How Edge AI Technology Is Redefining Smart Devices for the Future

Abstract: With the rapid growth of AI, we have seen a promising trend to migrate applications from cloud to edge devices for better user experience. Deep neural network training will be still in cloud due to its massive computation needs, but inference is better to be accomplished on the edge device due to it’s better availability, latency and privacy. However, providing better user experience will need both HW+SW technology breakthrough and optimize it from system perspective. MediaTek will share how edge AI technology is redefining smart devices to enable all the fascinating AI applications quickly to the market.

Abstracts

Track 1-1

Mentor's implementation flow for Edge smart IoT Mixed Signal ICs
Vincent Lai, Tanner Senior Applications Engineer, Mentor, a Siemens Business
Terence Chen, Worldwide Foundry Alliance Manager, CSD Nitro R&D Detail Routing, Mentor, a Siemens Business
This session will cover the latest enhancements to Mentor's complete design flow for analog/mixed-signal integrated circuits for IoT. The talk will highlight how Mentor's customers solved their design challenges using the flexibility of the Tanner platform.

Track 1-2

Solido Solutions – Delivering Variation Aware Design and Characterization Powered by Machine Learning.
Jiandong Ge, Solido Applications Engineering Consultant, Mentor, a Siemens Business
At lower nodes, increasing process variability requires innovative verification solution to ensure design quality robustness and meet the reduced time to market needs. With the acquisition of Solido Design Automation, Mentor became the leading provider of variation-aware design and characterization software with Solido's Variation Designer and ML Characterization Suite powered by proprietary machine learning technologies. In this session we will cover the latest capabilities in Solido Variation Designer and introduce Solido's new High-Sigma Verifier, a next-generation tool with algorithmic breakthroughs that make high-sigma verification faster and easier than ever before. We will also explore how library teams and digital teams benefit from ML Characterization Suite's machine learning methodology, enabling 2X+ runtime speedup for library characterization, and comprehensive validation of .LIBs within hours instead of weeks.

Track 1-3

Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform
Greg Curtis, AMS Verification Senior Product Manager, Mentor, a Siemens Business
In this session we provide an in-depth overview of Mentor's recently launched Symphony Mixed-Signal Platform. Symphony is the industry's fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across analog/digital (A/D) interfaces at all levels of the design hierarchy. Symphony's modular architecture leverages Mentor's Analog FastSPICE (AFS) circuit simulator for performance, capacity and accuracy. AFS is foundry certified up to 5nm FinFET-based processes, provides nanometer (nm) SPICE accuracy and capacity of 20M SPICE elements. AFS provides high performance circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Symphony powered by AFS provides customers with an average performance improvement of 2x over previous generation mixed-signal simulators along with best-in-class use model and advanced debug capabilities.

Track 1-4

Predicting Silicon Performance with High Accuracy Parasitic Extraction
Dicky Pan
Circuit designers want to achieve first time silicon success and one of the objectives is to get circuit simulation results that closely match silicon. This is the goal at any process node but is made more difficult when you consider new design requirements and process effects such as high frequency, FDSOI, FinFET devices, and 3DIC. Calibre xACT leverages 3D parasitic extraction technology to accurately model resistance, capacitance and inductance effects on the interconnect across multiple process corners to give designers confidence that their simulation results will match silicon performance.

Track 2-1

An Emulation Strategy for Artificial Intelligence and Machine Learning Devices
Philip Vanness, MED Product R&D Manager, Mentor, a Siemens Business
The emergence of Artificial Intelligence is the "next big thing" in the overall economy and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session. Supporting designs as big as 15 billion gates, Mentor's Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of machine learning benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average power. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of ASICs targeted for AI.

Track 2-2

DFT Enablement for AI device
Dragon Hsu, STS Senior AE Manager, Mentor, a Siemens Business
Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.

Track 2-3

Leveraging HLS IP and Reference Designs to Accelerate AI and Image/Signal Processing
Eric Chiu, Calypto Senior Applications Engineer, Mentor, a Siemens Business
To accelerate and ease the adoption of HLS, Catapult provides both building block HLS IP and various application reference designs written in C++ or SystemC that are designed to help deliver optimal QofR. This session will describe the available IP including the Math and DSP blocks available as open-source and the several reference designs, including 2-D convolution for image enhancements and two CNN (tinyYOLO) implementations for real-time object classification.

Track 2-4

How Advanced 3D Package Enables High Performance AI devices
Eddy Lu, Packaging Application Engineer, Mentor, a Siemens Business
Multi-function integration and HBM(Hight Bandwidth Memory) adoption make AI chip face the new challenge in package design, from IO planning, physical implementation, and down to verification. While silicon process is applied, the challenge is even greater. In this section, we will show how to overcome it with Mentor Xpedition Package Solution and Calibre 3DStack.

Track 3-1

Mentor Safe IC - End-to-end Functional Safety Solution addressing ISO-26262
Ann Keffer, Questa ICVS Product Marketing Manager, Mentor, a Siemens Business
Combining Mentor’s acquisition of Austemper Design Systems with existing Mentor and Siemens technologies, Mentor Safe IC provides the most comprehensive functional safety solution to bring increased automation for the entire IC functional safety flow. This session will provide an overview of Mentor Safety IC and how it can help increase your efficiency, shorten development cycles and reduce risk.

Track 3-2

Plan Driven and Requirements Driven Verification
Ann Keffer, Questa ICVS Product Marketing Manager, Mentor, a Siemens Business
Being able to author a test (verification) plan in a collaborative team environment is an important aspect of both Plan Driven and Requirements Driven methodologies. Once the test plan is defined, the common verification process is driven by ensuring that all the design features are being successfully tested. This is achieved by linking the tests and coverage model references defined within a test plan to the results of verification. The connection from the test plan to the design specification can be loosely bridged by the Verification Engineer. Alternatively, a requirements management system can hierarchically decompose system requirements through to hardware/software requirements, and onto test plans with verification results. This detailed level of traceability is a requirement of functional safety standards such as ISO26262 or DO-254. There may also be demands for traceability and audit between the design requirements and the VHDL/Verilog implementation. Ideally a smooth path should exist between the two methodologies, enabling a project to migrate from Plan Driven to Requirements Driven when it becomes necessary to fulfil the demands of safety critical standards. As well, an ideal solution should be agnostic to allow different data formats and tools to be supported. This session will highlight that Siemens and Mentor are in a great position and can offer a single solution to address both Plan Driven and Requirements Driven verification methodologies.

Track 3-3

The PAVE360 Program offers Chip-to-Vehicle verification continuity methods combining electronics, sensors and powertrain modeling for faster development of Safer Autonomous Vehicles
Philip Vanness, MED Product R&D Manager, Mentor, a Siemens Business
Sensing, Computing and Actuating components need to be included in any comprehensive verification process of autonomous vehicles. This presents a significant challenge, since it isn’t practical to do physical prototyping and use trial-and-error approach to find issues. And we can’t test safety and security thoroughly in a real, physical vehicle. The only way we can do an extensive verification job is to virtualize the entire system – environment and vehicle. This presentation will describe an innovative approach based on new methodology that combines verification and modeling of sensors, electronics and mechatronics components.

Track 3-4

The next level of test quality - silicon results
Dragon Hsu, STS Senior AE Manager, Mentor, a Siemens Business
The defection of defective devices during production test continues to become more demanding as automotive devices strive for single digit to zero defects per billion quality levels. Increasing needs for better test quality exist in many other industries where devices are more complex and expensive. Detecting defective devices during IC test has a significant impact on profitability and help avoid costly high level and system level tests. This talk will show the latest test quality methods employed in Automotive-grade ATPG and analog fault simulation for fault grading and pattern set effectiveness measures. We will demonstrate industry results for both methods.

Track 4-1

Plug and Play SoC DFT architecture
Jeff Fan, D2S Tessent Technical Marketing Engineer, Mentor, a Siemens Business
EDA companies used to supply discrete DFT tools for ATPG, or memory BIST, or other functions. Semiconductor DFT teams has traditionally been developed with the overall device in mind and were responsible for the SoC level integration. This is no longer possible. DFT for modern SoCs requires methodologies to address design scaling with plug-and-play principles and automation. The Tessent platform was developed over many years to solve these issues by providing one common tool and common database which includes various DFT functions such as ATPG or BIST as well as top level and hierarchical integration. As a result, users can achieve demanding schedule with automation and hierarchical/SoC level integration. The DFT methodologies described here are designed to address continued design scaling with plug-and-play principles and automation.

Track 4-2

Automated Formal Apps for SoC Verification
Stewart Li, Front End Solutions Senior AE Consultant, Mentor, a Siemens Business
As we have shown in prior Mentor Forums, one of the biggest developments in the verification world in has been the industry-wide adoption of automated, formal-based "apps". Requiring no prior knowledge of assertion-based verification or formal methods, formal apps combine automated, exhaustive formal analysis under-the-hood with well-documented methodologies focusing on specific, high-value verification challenges that are poorly served by other technologies. In this presentation we will show examples of where formal apps can accelerate specific SoC-scale verification tasks – both by reducing the required setup time and wall clock run time vs. traditional approaches.

Track 4-3

A Metrics-Driven Power Regression Methodology - Samsung's Power and Redundant Power analysis in RTL stage using PowerPro

Samsung: JinSuk Youn, Senior Engineer Manager, Samsung Foundry
JinSuk Youn received the Master degree in electrical engineering from Hanyang University, Seoul, Korea in 2002. He's working at Foundry Business, Samsung Electronics. His current research interests include RTL power reduction / estimation method.

Mentor: Thomas Lin, Calypto Senior Applications Engineer, Mentor, a Siemens Business

Design teams today need a true metrics-driven low power regression methodology that can measure their RTL IP ‘quality for power’. This methodology shall incorporates KPI's (Key Performance Indicators) that can be calculated, tracked and trended from very early stage RTL and be easily integrated into your regression environment to precisely point to which RTL IP's have potential power issues throughout RTL development cycle. Samsung Foundry have developed methodology (i.e. EDP) to check weakness of low power RTL code that Samsung collaborated with PowerPro.

Track 4-4

Have Your Cake and Eat It Too: Questa inFact PSS-Infused Apps Make the Most of Your UVM
CH Liu, Front End Solutions Senior Applications Engineer, Mentor, a Siemens Business
With the advent of the new Portable Test and Stimulus standard from Accellera, one of the most asked questions we hear is, "will Portable Stimulus replace UVM?" The answer is absolutely not. Portable Stimulus was conceived from the ground up to take advantage of UVM as one of the possible realization platforms for which tools may generate tests. This session will look at the PSS-UVM relationship and help attendees understand this important and powerful relationship.

Track 5-1

How to Reduce DRC Closure Time Enabling Faster SOC Tapeouts
Yoyo Li, D2S Calibre Foundry Technical Lead, Mentor, a Siemens Business
Often initial design iterations may have floor planning or placement issues. Running full blown sign-off DRC in such conditions will typically result in very long runtimes with millions of mostly meaningless results. To combat this challenge, the Calibre DRC team is introducing several new enhancements to simplify and speed such runs. In this session users will learn the details of these new features and best practices of when to use them. Moreover, P&R engineers spend a significant amount of time to fix last mile DRCs during sign-off DRC closure, which directly impacts their tapeout schedule. This session also presents how a customer uses Calibre RealTime Digital to reduce the turn-around time for sign-off DRC closure by 60% while optimizing their designs for timing, reliability and manufacturability constraints.

Track 5-2

Calibre and the Cloud: Unlocking Massive Scaling
Mentor: Shu-Wen Chang, Calibre Foundry Programs Director, Mentor, a Siemens Business

MS : Jacob Hsiao, Azure Product Marketing, Industry Business Development Manager, Microsoft

TSMC: Vivian Jiang, Technical Manager, Design Methodology & Service Marketing Program, TSMC
Vivian Jiang joined TSMC in 2015, and is currently responsible for TSMC OIP’s Cloud Alliance, creating synergy between Cloud service partners and EDA partners to fundamentally transform IC design via Cloud.
She brings over 19 years of experiences in the semiconductor industry, including IC design, ecosystem management and marketing. Ms. Jiang earns her B.S. degree in Electronic Engineering from Chung Yuan Christian University.

With ever larger foundry decks and 2X more transistors each new node, it is challenging to obtain the amount of on-premise computing resources needed to maintain fast DRC run times. In this session, you will hear experts from AMD, TSMC, and Microsoft Azure reveal the best known methods for using Calibre in the Cloud. This knowledge was obtained from real production use and collaboration with AMD on their latest designs using AMD EPYC servers in the Microsoft Azure Cloud.

Track 5-3

Calibre LVS: Innovation beyond a Verification Flow; A Complete Platform to Downstream Tools
Myron Lin, D2S Calibre Senior Foundry Technical Lead, Mentor, a Siemens Business
New methods to dramatically improve turn around time, and support PEX tools in advanced as well as established nodes, with new techniques to address more complex device parameters extraction that takes Calibre LVS from a circuit verification tool to a crucial high performance interface to parasitic extraction and downstream simulation tools. With the new design requirements and increasing process necessities, Calibre LVS is continuing to be the industry standard platform to achieve reliable and accurate silicon.

Track 5-4

Calibre PERC: Sign-Off Solutions for Circuit Reliability
Frank Feng, D2S Extraction Director, Mentor, a Siemens Business
Calibre PERC is a verification solution for circuit designers looking to validate their design is robust against common causes of electrical failure. Calibre PERC is a high-performance engine that has the performance/capacity/accuracy for verification at the IP, block, and full-chip level. Sign-off level foundry rule decks are available for Electrostatic Discharge and Latch-Up (ESD/LUP) verification as well as other solutions for Voltage-Aware DRC, Electrical OverStress (EOS), and Analog Constraint Checks.

Lucky Draw

活動當日課程結束後，只要填寫問卷就有機會獲得多項大獎，獎項包括

Microsoft Surface Go 10 吋平板筆電
Dyson v7 Fluffy Origin 無線吸塵器
Apple AirPods 搭配無線充電盒
JBL Charge 4 防水攜帶式藍牙喇叭
Samsung Galaxy Watch Active智慧型手錶

現場抽獎，聽完豐富的課程後千萬不要忘記填寫問卷，幸運大獎就等您領取!!